1. Technical Field of the Invention
The present invention relates to a digital Delay Lock Loop (DLL) with an adaptable Clock Adjust Block for fast locking time.
2. Description of Related Art
Phase Locked Loops (PLL's) and Delay Locked Loops (DLL's) are very extensively employed in bigger chips like a System on Chip (SOC), a microprocessor, a memory, and the like, in order to cancel the on chip clock amplification and buffering delays, and improve the I/O timing margins. However, the increasing clock speeds and increasing levels of complexity in digital circuits create a hostile operating environment for the phase alignment circuits. The supply and substrate noise resulting from the switching of digital circuits can affect the PLL or DLL operation and result in output clock jitter that subtracts from the I/O timing margins.
For example, in Synchronous Dynamic Random Access Memory (SDRAM) applications, as frequencies approach 200 MHz, the inherent analog delay between an external system or reference clock and valid output data time is becoming a crucial constraint. Such a delay of, for example, 4-10 ns is large enough to make a following clock cycle overlap the data, i.e., the delay becomes large enough for data not to be ready at the output during one cycle, and it essentially becomes “off-sync”. This inherent internal delay must therefore be accelerated according to the necessary frequency but in a controlled fashion. The problem translates into a synchronization task between the internal clock, which controls the output path, and the correct edge of the external clock.
Analog DLLs have been employed in the past to perform synchronization. Analog DLLs are comprised of a delay chain having delay of its elements varied by analog bias voltages supplied by a phase detector. In digital systems such as memories, microprocessors and application specific integrated circuits, these types of DLLs introduce analog design complications in a mainly digital design and therefore are avoided.
To overcome the above-mentioned complications, digital DLLs were developed which used a digitally adjustable delay line. Digital information is used to either include or exclude a certain number of delay elements within a delay chain. Although digital DLLs have a much higher jitter than analog DLLs, their ease of implementation in the digital system makes them a preferred solution in most digital applications.
In applications where no clock synthesis is required, DLLs offer an attractive alternative to PLLs due to their better jitter performance, inherent stability, and simpler design. The main disadvantage of conventional DLLs, however, is their limited phase capture range.
FIG. 1 shows simplified block diagram of digital DLL. The digital DLL includes a digital Coarse tuning section 10 receiving the external clock and control signals for generating a delayed output clock; a digital Fine tuning section 11 receiving control signals and the output of the digital Coarse tuning section 10 for further tuning; and a control block 12 receiving external and internal clock for generating control signals for configuring the tuning sections 10 and 11. These tuning sections 10 and 11 use variable delay chains containing a plurality of delay cells connected in series. Two distinct types of delay cells are used in these tuning sections 10 and 11 where each delay cell is exclusively used in a particular tuning block namely Coarse tuning section 10 and Fine-tuning section 11. The Coarse tuning section 10 contains delay cells with larger delays as compared to delay cells in the Fine-tuning section 11. The total delay of the delay chain in the Fine-tuning section 11 is equal to the delay of one delay cell in Coarse tuning section 10.
Each delay cell in these chains has an associated tap and this tap is used to select a specified delay, which is the sum of the delays of delay cells till the corresponding tap point. The tap selection for Coarse and Fine-tuning sections 10 and 11 is done by the Control block 12, which receives internal and external clock and produces control signals for tap selection in tuning sections. The external clock is used as the reference clock in this block. The control block uses ring counters and edge detection circuitry to generate the control signals for tap selection.
However, the inherent problem of this DLL setup comes into light when the clock tree delay is more than a clock period. In this case, the DLL will never be locked if the clock to the control block is same as the external clock. The problem is illustrated by using the example given in FIG. 2.
Consider a situation in which the clock tree delay is equal to 3 clock periods. Due to this delay, whichever tap is selected by the control block 12 its effect will be visible on the feedback clock only after 3 clock periods. Hence any decision (Right Shift/Left Shift/Lock) will be taken 3 clock periods after the tap is selected. But until that decision is taken 3 more taps would have been selected, as the control block counter would have counted 3 more clock cycles. This is a source of potential error. From the waveforms of FIG. 2 it is clear that any decision, which is taken with respect to the Feedback Clock corresponding to TAPx, will be reflected only when TAP (x+2) is selected. Hence, a correct decision will never be taken. The whole problem arises because the decision for the tap selection is taken before the feedback clock gives any indication. This tap selection is controlled by the control block 12, which is operating at the input clock frequency. Thus, if the clock to the Control block 12 is divided such that no further tap is selected till the output clock arrives at the feedback clock terminal, the problem is solved.
Prior art United States Published Application for Patent No. 2001/0005337, describes a DLL for use in a synchronous memory device. In this prior art reference, a fixed divider is used for the control clock and as a result, the DLL acts properly if the feedback delay is less than N clock cycles, where N is the division factor of the fixed divider. For a control clock operating at high frequency, this translates into an upper limit on delay allowed in terms of clock cycles. Another major drawback of the prior art DLL is seen at low clock frequency operation. At low clock frequency, the period of the clock is long and as a result, the clock tree delay may be less than one clock cycle. As a result, the fixed divider unnecessarily slows down the control block operation by introducing a control clock operating at even lower frequency. Slower control block operation results in an unnecessary slow down of the locking operation in DLL. In conclusion, an undesirable characteristic of the prior art DLL with a fixed divider is its dependence on the external clock frequency and the clock tree delay. It is also observed that the prior art uses significant hardware resources, which is undesirable in silicon implementation.
To obviate the aforesaid drawbacks a need exists to provide fast locking in digital DLL.
Another need is to provide an area efficient solution.
Yet another need is to remove the clock tree delay dependency.